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| NCP3020A, NCP3020B Product Preview Synchronous PWM Controller The NCP3020 is a PWM device designed to operate from a wide input range and is capable of producing an output voltage as low as 0.6 V. The NCP3020A provides integrated gate drivers and an internally set 300 kHz oscillator (600 kHz for the NCP3020B). The NCP3020 has an externally compensated transconductance error amplifier with an internally fixed soft-start. Protection features include lossless current limit and Short Circuit Protection, Output Overvoltage protection, Output Undervoltage protection, and Input Undervoltage Lockout. The NCP3020 is currently available in a SOIC-8 package. Features http://onsemi.com 8 1 SOIC-8 NB CASE 751 * * * * * * * * * * Input Voltage Range from 4.5 V to 28 V Switching and Synchronous Rectifier Drives with >1.0 A Capability 300 kHz Operation (NCP3020B - 600 kHz) 0.6 1.0% Reference Voltage Internally Programmed 6.8 ms Soft-Start (NCP3020B - 3.4 ms) Current Limit and Short Circuit Protection Transconductance Amplifier with External Compensation Input Undervoltage Lockout Output Overvoltage and UndervoltageDetection This is a Pb-Free Device MARKING DIAGRAM 8 XXXXX ALYW G 1 XXXXX A L Y W G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package 4.5-28 V CIN CBST VCC BST HSDR COMP RC CC2 CC1 VSW LSDR GND RISET Q2 RFB1 RFB2 C0 Q1 L0 Vout PIN CONNECTIONS VCC COMP FB GND BST HSDR VSW LSDR ORDERING INFORMATION Device NCP3020ADR2G NCP3020BDR2G Package Shipping SOIC-8 2500 / Tape & Reel (Pb-Free) SOIC-8 2500 / Tape & Reel (Pb-Free) FB Figure 1. Typical Application Circuit For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. (c) Semiconductor Components Industries, LLC, 2009 November, 2009 - Rev. P1 1 Publication Order Number: NCP3020/D NCP3020A, NCP3020B VCC INTERNAL BIAS POR/STARTUP VC THERMAL SD BOOST CLAMP BST OSCILLATOR CLK/ DMAX/ SOFT START RAMP 1.5 V + - GATE DRIVE LOGIC LEVEL SHIFT VCC CURRENT LIMIT ISET VC SAMPLE & HOLD HSDR VSW COMP REF OTA FB + - + - PWM COMP LSDR OOV OUV BST_CHRG GND Figure 2. NCP3020 Block Diagram PIN FUNCTION DESCRIPTION Pin 1 2 Pin Name VCC COMP Description The VCC pin is the main voltage supply input. It is also used in conjunction with the VSW pin to sense current in the high side MOSFET. The COMP pin connects to the output of the Operational Transconductance Amplifier (OTA) and the positive terminal of the PWM comparator. This pin is used in conjunction with the FB pin to compensate the voltage mode control feedback loop. The FB pin is connected to the inverting input of the OTA. This pin is used in conjunction with the COMP pin to compensate the voltage mode control feedback loop. Ground Pin The LSDR pin is connected to the output of the low side driver which connects to the gate of the low side N-FET. It is also used to set the threshold of the current limit circuit (ISET) by connecting a resistor from LSDR to GND. The VSW pin is the return path for the high side driver. It is also used in conjunction with the VCC pin to sense current in the high side MOSFET. The HSDR pin is connected to the output of the high side driver which connects to the gate of the high side N-FET. The BST pin is the supply rail for the gate drivers. A capacitor must be connected between this pin and the VSW pin. 3 4 5 FB GND LSDR 6 7 8 VSW HSDR BST http://onsemi.com 2 NCP3020A, NCP3020B ABSOLUTE MAXIMUM RATINGS (measured vs. GND pin 8, unless otherwise noted) Rating High Side Drive Boost Pin Boost to VSW differential voltage COMP Feedback High-Side Driver Output Low-Side Driver Output Main Supply Voltage Input Switch Node Voltage Maximum Average Current VCC, BST, HSDRV, LSDRV, VSW, GND Operating Junction Temperature Range (Note 1) Maximum Junction Temperature Storage Temperature Range Thermal Characteristics (Note 2) TSSOP-14 Plastic Package Maximum Power Dissipation @ TA = 25C Thermal Resistance Junction-to-Air Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb-Free (Note 3) Moisture Sensitivity Level (Note 4) ESD Withstand Voltage (Note 5) Human Body Model Machine Model Latch-up Current (TA = 85C) (Note 6) Symbol BST BST-VSW COMP FB HSDR LSDR VCC VSW Imax TJ TJ(MAX) Tstg VMAX 45 13.2 5.5 5.5 40 13.2 40 40 130 -40 to +140 +150 -55 to +150 VMIN -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.6 Unit V V V V V V V V mA C C C PD RqJA RF MSL Vesd 0.5 190 260 Peak 3 2.0 200 100 W C/W C - kV V mA Lu Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The maximum package power dissipation limit must not be exceeded. PD + 2. 3. 4. 5. T J(max) * T A R qJA When mounted on minimum recommended FR-4 or G-10 board 60-180 seconds minimum above 237C. Moisture Sensitivity Level (MSL): 3 per IPC/JEDEC standard: J-STD-020A. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) per JEDEC standard: JESD22-A114. Machine Model (MM) per JEDEC standard: JESD22-A115. 6. Latch-up Current Maximum Rating: per JEDEC standard: JESD78 http://onsemi.com 3 NCP3020A, NCP3020B ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic Input Voltage Range SUPPLY CURRENT VCC Supply Current VCC Supply Current NCP3020A NCP3020B VFB = 0.55 V, Switching, VCC = 4.5 V VFB = 0.55 V, Switching, VCC = 28 V VFB = 0.55 V, Switching, VCC = 4.5 V VFB = 0.55 V, Switching, VCC = 28 V UNDER VOLTAGE LOCKOUT UVLO Rising Threshold UVLO Falling Threshold OSCILLATOR Oscillator Frequency Oscillator Frequency Ramp-Amplitude Voltage Ramp Valley Voltage PWM Minimum Duty Cycle Maximum Duty Cycle Soft Start Ramp Time NCP3020A NCP3020B VFB = VCOMP (Note 7) - 80 - - 7.0 84 6.8 3.4 - - - - % % ms NCP3020A NCP3020B TJ = +25C, 4.5 V v VCC v 28 V TJ = -40C to +125C, 4.5 V v VCC v 28 V TJ = +25C, 4.5 V v VCC v 28 V TJ = -40C to +125C, 4.5 V v VCC v 28 V Vpeak - Valley 250 240 TBD TBD - 0.46 300 300 600 600 1.5 0.71 350 360 TBD TBD - 0.85 kHz kHz kHz kHz V V VCC Rising Edge VCC Falling Edge 4.0 3.5 4.3 3.9 4.7 4.3 V V - - - - 5.1 6.2 6.8 8.3 8.0 11 TBD TBD mA mA mA mA Conditions - Min 4.5 Typ Max 28 Unit V ERROR AMPLIFIER (GM) Transconductance Open Loop dc Gain Output Source Current Output Sink Current FB Input Bias Current Feedback Voltage COMP High Voltage COMP Low Voltage OUTPUT VOLTAGE FAULTS Feedback OOV Threshold Feedback OUV Threshold OVERCURRENT ISET Source Current Current Limit Set Voltage (Note 8) RSET = 22.5 kW TBD TBD 12.5 298 TBD TBD mA mV 0.68 0.42 0.75 0.45 0.82 0.48 V V TJ = 25 C 4.5 V < VIN < 28 V, -40C < TJ < +125C VFB = 0 V VFB = 2 V (Notes 7 and 9) VFB = 545 mV VFB = 655 mV 0.9 - 45 45 - 0.594 0.588 4.0 - 1.3 70 70 70 0.5 0.6 0.6 4.4 65 1.7 - 100 100 500 0.606 0.612 5.0 200 mS dB mA mA nA V V V mV 7. Guaranteed by design. 8. The voltage sensed across the high side MOSFET during conduction. 9. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. 10. This is not a protection feature. http://onsemi.com 4 NCP3020A, NCP3020B ELECTRICAL CHARACTERISTICS (-40C < TJ < +125C, VCC = 12 V, for min/max values unless otherwise noted) Characteristic GATE DRIVERS AND BOOST CLAMP HSDRV Pullup Resistance VCC = 8 V, VBST = 7.5 V VSW = GND 100 mA out of HSDR pin VCC = 8 V, VBST = 7.5 V VSW = GND 100 mA into HSDR pin VCC = 8 V, VBST = 7.5 V VSW = GND 100 mA out of LSDR pin VCC = 8 V, VBST = 7.5 V VSW = GND 100 mA into LSDR pin VCC = 8 V, VBST = 7.5 V VCC = 8 V, VBST = 7.5 V VIN = 12 V, VSW = GND, VCOMP = 1.3 V (Notes 7 and 10) (Notes 7 and 10) 5.0 10.5 20 W Conditions Min Typ Max Unit HSDRV Source HSDRV Pulldown Resistance - 2.5 0.7 5.0 - 10.5 A W HSDRV Sink LSDRV Pullup Resistance - 5.0 1.5 8.9 - 15 A W LSDRV Source LSDRV Pulldown Resistance - 1.0 0.85 2.8 - 6.0 A W LSDRV Sink HSDRV falling to LSDRV Rising Delay LSDRV Falling to HSDRV Rising Delay Boost Clamp Voltage THERMAL SHUTDOWN Thermal Shutdown Hysteresis - 60 60 6.0 - - 2.7 76 84 7.5 175 20 - 100 100 9.6 - - A ns ns V C C 7. Guaranteed by design. 8. The voltage sensed across the high side MOSFET during conduction. 9. This assumes 100 pF capacitance to ground on the COMP Pin and a typical internal Ro of > 10 MW. 10. This is not a protection feature. http://onsemi.com 5 NCP3020A, NCP3020B TYPICAL PERFORMANCE CHARACTERISTICS 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0 2 4 Iout (A) Typical Application Circuit Figure 37 6 8 10 18 V 12 V 15 V Vout (V) 3.27 9V 3.265 3.26 3.255 3.25 Typical Application Circuit Figure 37 0 2 4 Iout (A) 6 8 10 12 V 3.28 9V 3.275 15 V 18 V Figure 3. Efficiency vs. Output Current and Input Voltage Figure 4. Load Regulation vs. Input Voltage Input = 9 V, Output = 3.3 V, Load = 10 A C4 (Green) = VIN, C2 (Red) = VOUT C1 (Yellow) = VSW, C3 (Blue) = HSDR Input = 18 V, Output = 3.3 V, Load = 10 A C4 (Green) = VIN, C2 (Red) = VOUT C1 (Yellow) = VSW, C3 (Blue) = HSDR Figure 5. Switching Waveforms (VIN = 9 V) 606 604 602 VFB (mV) 600 598 596 594 -40 -25 -10 340 330 320 fSW (kHz) VCC = 12 V, 28 V 310 300 290 280 270 5 20 35 50 65 80 95 110 125 Figure 6. Switching Waveforms (VIN = 18 V) NCP3020A VCC = 12 V, 28 V VCC = 5 V VCC = 5 V 260 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) Figure 7. Feedback Reference Voltage vs. Input Voltage and Temperature Figure 8. Switching Frequency vs. Input Voltage and Temperature http://onsemi.com 6 NCP3020A, NCP3020B TYPICAL PERFORMANCE CHARACTERISTICS 660 640 620 fSW (kHz) gm (ms) 600 580 560 540 -40 -25 -10 VCC = 12 V, 28 V VCC = 5 V NCP3020B 1.50 1.45 1.40 1.35 1.30 1.25 1.20 1.15 1.10 1.05 5 20 35 50 65 80 95 110 125 1.00 -40 -25 -10 5 20 35 50 65 80 95 110 125 VCC = 12 V, 28 V VCC = 5 V TEMPERATURE (C) TEMPERATURE (C) Figure 9. Switching Frequency vs. Input Voltage and Temperature 4.4 4.3 4.2 OOV (mV) UVLO (V) 4.1 4.0 3.9 3.8 -40 -25 -10 800 760 UVLO Rising 720 680 640 600 560 520 480 UVLO Falling 5 20 35 50 65 80 95 110 125 440 Figure 10. Transconductance vs. Input Voltage and Temperature OOV, VCC = 5 - 28 V OOV, VCC = 5 - 28 V 400 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) TEMPERATURE (C) Figure 11. Input Undervoltage Lockout vs. Temperature 7.5 7.0 ICC, SWITCHING (mA) 6.5 6.0 5.5 5.0 4.5 4.0 -40 -25 -10 5 20 35 50 65 80 VCC = 28 V VCC = 12 V VCC = 5 V Figure 12. Output Overvoltage Lockout vs. Input Voltage and Temperature TBD NCP3020A 95 110 125 TEMPERATURE (C) Figure 13. Supply Current vs. Input Voltage and Temperature Figure 14. Supply Current vs. Input Voltage and Temperature http://onsemi.com 7 NCP3020A, NCP3020B TYPICAL PERFORMANCE CHARACTERISTICS 1000 950 NCP3020A tSoft-Start (ms) VALLEY VOLTAGE (mV) 900 850 800 750 700 650 600 550 500 450 400 -40 -25 -10 VCC = 5 - 28 V 8.0 7.5 NCP3020A 7.0 6.5 6.0 5.5 VCC = 5 V VCC = 12 V, 28 V 5 20 35 50 65 80 NCP3020B VCC = 5 V VCC = 12 V, 28 V 6.0 5.5 5.0 4.5 4.0 3.5 3.0 95 110 125 NCP3020B tSoft-Start (ms) 5 20 35 50 65 80 5.0 95 110 125 -40 -25 -10 TEMPERATURE (C) TEMPERATURE (C) Figure 15. Ramp Valley Voltage vs. Input Voltage and Temperature 14 13.8 Figure 16. Soft-Start Time vs. Input Voltage and Temperature ISET (mA) 13.6 13.4 13.2 13 -40 -25 -10 VCC = 12 V, 28 V VCC = 5 V 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) Input = 12 V, Output = 3.3 V, Load = 5 A C1 (Yellow) = VIN, C4 (Green) = VOUT C2 (Red) = HSDR, C3 (Blue) = LSDR Figure 17. Current Limit Set Current vs. Temperature Figure 18. Soft-Start Waveforms Input = 12 V, Output = 3.3 V, Load = 5 A C1 (Yellow) = VIN, C4 (Green) = VOUT C2 (Red) = HSDR, C3 (Blue) = LSDR Input = 12 V C1 (Yellow) = FB, C3 (Blue) = LSDR C2 (Red) = HSDR, C4 (Green) = VIN Figure 19. Shutdown Waveforms Figure 20. Startup into a Current Limit http://onsemi.com 8 NCP3020A, NCP3020B DETAILED DESCRIPTION OVERVIEW The NCP3020A/B operates as a 300/600 kHz, voltage mode, pulse width modulated, (PWM) synchronous buck converter. It drives high-side and low-side N-channel power MOSFETs. The NCP3020 incorporates an internal boost circuit consisting of a boost clamp and boost diode to provide supply voltage for the high side MOSFET gate driver. The NCP3020 also integrates several protection features including input undervoltage lockout (UVLO), output undervoltage (OUV), output overvoltage (OOV), adjustable high-side current limit (ISET and ILIM), and thermal shutdown (TSD). The operational transconductance amplifier (OTA) provides a high gain error signal from Vout which is compared to the internal 1.5 V pk-pk ramp signal to set the duty cycle converter using the PWM comparator. The high side switch is turned on by the positive edge of the clock cycle going into the PWM comparator and flip flop following a non-overlap time. The high side switch is turned off when the PWM comparator output is tripped by the modulator ramp signal reaching a threshold level established by the error amplifier. The gate driver stage incorporates symmetrical fixed non- overlap time between the high-side and low-side MOSFET gate drives to prevent cross conduction of the power MOSFET's. POR and UVLO The device contains an internal Power On Reset (POR) and input Undervoltage Lockout (UVLO) that inhibits the internal logic and the output stage from operating until VCC reaches its respective predefined voltage levels (4.3 V typical). Startup and Shutdown Once enable is asserted the device begins its startup process. Closed-loop soft-start begins after a 400 ms delay wherein the boost capacitor is charged, and the current limit threshold is set. During the 400 ms delay the OTA output is set to 700 mV which is just below the low point of the internal ramp. This is done to reduce delays and to ensure a consistent pre-soft-start condition. The device increases the internal reference from 0 V to 0.6 V in 32 discrete steps while maintaining closed loop regulation at each step. Some overshoot may be evident at the start of each step depending on the voltage loop phase margin and bandwidth. See Figure 21. The total soft-start time is 6.8 ms for the NCP3020A and 3.4 ms for the NCP3020B. 0.6 V Output Voltage 18.75 mV Steps 32 Voltage Steps Internal Reference Voltage Internal Ramp OTA Output 0 .7V 0V Output Voltage Internal Reference Voltage 0 12 34 567 8 91 111 11 11 112 2 22 222 22 23 33 0 123 45 67 890 1 23 456 78 90 12 Switch Node OTA Output Figure 21. Soft-Start Details http://onsemi.com 9 NCP3020A, NCP3020B OOV and OUV The output voltage of the buck converter is monitored at the Feedback pin of the output power stage. Two comparators are placed on the feedback node of the OTA to monitor the operating window of the feedback voltage as shown in Figures 22 and 23. All comparator outputs are ignored during the soft-start sequence as soft-start is regulated by the OTA and false trips would be generated. After the soft-start period has ended, if the feedback is below the reference voltage of comparator 2 (VFB < 0.45 V), the output is considered "undervoltage" and the device will initiate a restart. When the feedback pin voltage rises between the reference voltages of comparator 1 and comparator 2 (0.45 < VFB < 0.75), then the output voltage is considered "Power Good." Finally, if the feedback voltage is greater than comparator 1 (VFB > 0.75 V), the output voltage is considered "overvoltage," and the device will latch off. To clear a latch fault, input voltage must be recycled. Graphical representation of the OOV and OUV is shown in Figures 24 and 25. Soft Start Complete Vref*125% Comparator 1 Restart LOGIC FB Latch off Vref*75% Vref = 0.6 V Comparator 2 Figure 22. OOV and OUV Circuit Diagram OOVP & Power Good = 0 Hysteresis = 5 mV Power Good = 1 Voov = Vref * 125% Power Not good High Vref = 0.6 V Power Good = 1 Hysteresis = 5 mV OUVP & Power Good = 0 Power Not Good Low Voov = Vref * 75% Figure 23. OOV and OUV Window Diagram http://onsemi.com 10 NCP3020A, NCP3020B 0.75 V (vref *125%) 0.6 V (vref *100%) 0.45 V (vref *75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 24. Powerup Sequence and Overvoltage Latch 0.75 V (vref *125%) 0.6 V (vref *100%) 0.45 V (vref * 75%) FB Voltage Latch off Reinitiate Softstart Softstart Complete Figure 25. Powerup Sequence and Undervoltage Soft-Start http://onsemi.com 11 NCP3020A, NCP3020B CURRENT LIMIT AND CURRENT LIMIT SET Overview The device uses the voltage drop across the High Side MOSFET during the on time to sense inductor current. The ILimit block consists of a voltage comparator circuit which compares the differential voltage across the VCC Pin and the VSW Pin with a resistor settable voltage reference. The sense portion of the circuit is only active while the HS MOSFET is turned ON. VIN VCC Ilim Out VSense Itrip Ref HSDR VSW Switch Cap CONTROL Iset 12.5uA LSDR DAC / COUNTER 6 Vset RSet Itrip Ref-63 Steps, 3.255 mV/step Figure 26. Iset / ILimit Block Diagram Current Limit Set The ILimit comparator reference is set during the startup sequence by forcing a 12.5 mA current through the low side gate drive resistor. The gate drive output will rise to a voltage level shown in the equation below: V set + I set * R set (eq. 1) Where ISET is 12.5 mA and RSET is the gate to source resistor on the low side MOSFET. This resistor is normally installed to prevent MOSFET leakage from causing unwanted turn on of the low side MOSFET. In this case, the resistor is also used to set the ILimit trip level reference through the ILimit DAC. The Iset process takes approximately 350 ms to complete prior to Soft-Start stepping. The scaled voltage level across the ISET resistor is converted to a 6 bit digital value and stored as the trip value. The binary ILimit value is scaled and converted to the analog ILimit reference voltage through a DAC counter. The DAC has 54 steps in 3.255 mV increments equating to a maximum sense voltage of 176 mV. During the Iset period prior to Soft-Start, the DAC counter increments the reference on the ISET comparator until it crosses the VSET voltage and holds the DAC reference output to that count value. This voltage is translated to the ILimit comparator during the ISense portion of the switching cycle through the switch cap circuit. See Figure 26. Current Sense Cycle Figure 27 shows how the current is sampled as it relates to the switching cycle. Current level 1 in Figure 27 represents a condition that will not cause a fault. Current level 2 represents a condition that will cause a fault. The sense circuit is allowed to operate below the 3/4 point of a given switching cycle. A given switching cycle's 3/4 Ton time is defined by the prior cycle's Ton and is quantized in 10 ns steps. A fault occurs if the sensed MOSFET voltage exceeds the DAC reference within the 3/4 time window of the switching cycle. http://onsemi.com 12 NCP3020A, NCP3020B Trip: Vsense > Itrip Ref at 3/4 Point No Trip: Vsense < Itrip Ref at 3/4 Point Itrip Ref Vsense Ton-2 3/4 Ton-1 3/4 Current Level 1 Current Level 2 3/4 Point Determined by Prior Cycle 1/4 1/2 3/4 1/4 1/2 3/4 Ton-1 Ton Each switching cycle's Ton is counted in 10 nS time steps. The 3/4 sample time value is held and used for the following cycle's limit sample time Figure 27. ILimit Trip Point Description Soft-Start Current limit Boost Clamp Functionality During soft-start the ISET value is doubled to allow for inrush current to charge the output capacitance. The DAC reference is set back to its normal value after soft-start has completed. The ILimit block can lose accuracy if there is excessive VSW voltage ringing that extends beyond the 1/2 point of the high-side transistor on-time. Proper snubber design and keeping the ratio of ripple current and load current in the 10-30% range can help alleviate this as well. Current Limit VSW Ringing A current limit trip results in completion of one switching cycle and subsequently half of another cycle Ton to account for negative inductor current that might have caused negative potentials on the output. Subsequently the power MOSFETs are both turned off and a 4 soft-start time period wait passes before another soft-start cycle is attempted. Iave vs Trip Point The boost circuit requires an external capacitor connected between the BST and VSW pins to store charge for supplying the high and low-side gate driver voltage. This clamp circuit limits the driver voltage to typically 7.5 V when VIN > 9 V, otherwise this internal regulator is in dropout and typically VIN - 1.25 V. The boost circuit regulates the gate driver output voltage and acts as a switching diode. A simplified diagram of the boost circuit is shown in Figure 28. While the switch node is grounded, the sampling circuit samples the voltage at the boost pin, and regulates the boost capacitor voltage. The sampling circuit stores the boost voltage while the VSW is high and the linear regulator output transistor is reversed biased. VIN 8.9V The average load trip current versus RSET value is shown the equation below: I AveTRIP + I set R set R DS(on) * 1 V IN * V OUT 4 L V OUT V IN 1 F SW (eq. 2) Switch Sampling Circuit BST VSW LSDR Where: L = inductance (H) ISET = 12.5 mA RSET = gate to source resistance (W) RDS(on) = On resistance of the HS MOSFET (W) VIN = Input Voltage (V) VOUT = Output Voltage (V) FSW = Switching Frequency (Hz) 13 Figure 28. Boost Circuit Reduced sampling time occurs at high duty cycles where the low side MOSFET is off for the majority of the switching period. Reduced sampling time causes errors in the regulated voltage on the boost pin. High duty cycle / input voltage induced sampling errors can result in increased http://onsemi.com NCP3020A, NCP3020B boost ripple voltage or higher than desired DC boost voltage. Figure 29 outlines all operating regions. The recommended operating conditions are shown in Region 1 (Green) where a 0.1 mF, 25 V ceramic capacitor can be placed on the boost pin without causing damage to the device or MOSFETS. Larger boost ripple voltage occurring over several switching cycles is shown in Region 2 (Yellow). The boost ripple frequency is dependant on the output capacitance selected. The ripple voltage will not damage the device or $12 V gate rated MOSFETs. Boost Voltage Levels Normal Operation Increased Boost Ripple (Still in Specification) Increased Boost Ripple Capacitor Optimization Required Conditions where maximum boost ripple voltage could damage the device or $12 V gate rated MOSFETs can be seen in Region 3 (Orange). Placing a boost capacitor that is no greater than 10X the input capacitance of the high side MOSFET on the boost pin limits the maximum boost voltage < 12 V. The typical drive waveforms for Regions 1, 2 and 3 (green, yellow, and orange) regions of Figure 29 are shown in Figure 30. 28 26 24 22 In p u t V o lt a g e 20 18 16 14 12 10 8 6 4 2 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 11.5V 71% Region 1 Region 2 Maxi mum Max Duty Duty Cycle Cycle 22V Region 3 Duty Cycle Figure 29. Safe Operating Area for Boost Voltage with a 0.1 mF Capacitor http://onsemi.com 14 NCP3020A, NCP3020B VIN 7.5V VBOOST 7.5V Maximum Normal VIN 7.5V 0V VBOOST 7.5V Maximum Normal VIN 7.5V 0V VBOOST 7.5V 0V Figure 30. Typical Waveforms for the Green, Yellow, and Orange Region To illustrate, a 0.1 mF boost capacitor operating at > 80% duty cycle and > 22.5 V input voltage will exceed the specifications for the driver supply voltage. See Figure 31. http://onsemi.com 15 NCP3020A, NCP3020B Boost Voltage 18 16 14 12 Boost Voltage (V) 10 8 6 4 2 0 4.5 Voltage Ripple Maximum Allowable Voltage Maximum Boost Voltage 6.5 8.5 10.5 12.5 14.5 16.5 18.5 Input Voltage (V) 20.5 22.5 24.5 26.5 (Clarity on Boost Max and Ripple Def) Figure 31. Boost Voltage at 80% Duty Cycle Inductor Selection T ON T T OFF T V OUT V IN (eq. 5) When selecting the inductor, it is important to know the input and output requirements. Some example conditions are listed below to assist in the process. Table 1. DESIGN PARAMETERS Design Parameter Input Voltage Nominal Input Voltage Output Voltage Input ripple voltage Output ripple voltage Output current rating Operating frequency (VIN) (VIN) (VOUT) (VINRIPPLE) (VOUTRIPPLE) (IOUT) (Fsw) Example Value 9 V to 18 V 12 V 3.3V 300 mV 50 mV 10A 300 kHz D+ D+ (* D + (eq. 4) V OUT ) V LSD V IN * V HSD ) V LSD 3.3 V 12 V [D+ 27.5% + The ratio of ripple current to maximum output current simplifies the equations used for inductor selection. The formula for this is given in Equation 6. ra + DI I OUT (eq. 6) A buck converter produces input voltage (VIN) pulses that are LC filtered to produce a lower dc output voltage (VOUT). The output voltage can be changed by modifying the on time relative to the switching period (T) or switching frequency. The ratio of high side switch on time to the switching period is called duty cycle (D). Duty cycle can also be calculated using VOUT, VIN, the low side switch voltage drop VLSD, and the High side switch voltage drop VHSD. F+ 1 T (eq. 3) The designer should employ a rule of thumb where the percentage of ripple current in the inductor lies between 10% and 40%. When using ceramic output capacitors the ripple current can be greater thus a user might select a higher ripple current, but when using electrolytic capacitors a lower ripple current will result in lower output ripple. Now, acceptable values of inductance for a design can be calculated using Equation 7. L+ V OUT I OUT @ ra @ F SW 12 V 10 A @ 32.5% @ 300 kHz @ (1 * D) 3.3 mH (eq. 7) + @ (1 * 27.5%) http://onsemi.com 16 NCP3020A, NCP3020B The relationship between ra and L for this design example is shown in Figure 32. 18 17 16 18 V 15 14 15 V 13 12 11 10 12 V 9 8 7 6 5 4 9V 3 2 1 0 10% 15% 20% 25% VIN, (V) expense of higher ripple current. The peak-to-peak ripple current for the NCP3020A is given by the following equation: I PP + V OUT(1 * D) L OUT @ F SW (eq. 11) Vout = 3.3 V 30% 35% 40% Ipp is the peak to peak current of the inductor. From this equation it is clear that the ripple current increases as LOUT decreases, emphasizing the trade-off between dynamic response and ripple current. The power dissipation of an inductor consists of both copper and core losses. The copper losses can be further categorized into dc losses and ac losses. A good first order approximation of the inductor losses can be made using the DC resistance as they usually contribute to 90% of the losses of the inductor shown below: LP CU + I RMS 2 @ DCR (eq. 12) L, INDUCTANCE (mH) Figure 32. Ripple Current Ration vs. Inductance To keep within the bounds of the parts maximum rating, calculate the RMS current and peak current. I RMS + I OUT @ + 10 A @ 1 ) ra 10.04 A 12 2 1 ) 32.5% 12 2 The core losses and ac copper losses will depend on the geometry of the selected core, core material, and wire used. Most vendors will provide the appropriate information to make accurate calculations of the power dissipation then the total inductor losses can be capture buy the equation below: LP tot + LP CU_DC ) LP CU_AC ) LP Core (eq. 13) (eq. 8) Component Selection Input Capacitor Selection ra 32.5% I PK + I OUT @ 1 ) 11.63 A + 10 A @ 1 ) 2 2 (eq. 9) An inductor for this example would be around 3.3 mH and should support an rms current of 10.04 A and a peak current of 11.63 A. The final selection of an output inductor has both mechanical and electrical considerations. From a mechanical perspective, smaller inductor values generally correspond to smaller physical size. Since the inductor is often one of the largest components in the regulation system, a minimum inductor value is particularly important in space-constrained applications. From an electrical perspective, the maximum current slew rate through the output inductor for a buck regulator is given by Equation 10. SlewRate LOUT + V IN * V OUT L OUT 1.5 12 V * 3.3 V A + ms 5.8 mH (eq. 10) The input capacitor has to sustain the ripple current produced during the on time of the upper MOSFET, so it must have a low ESR to minimize the losses. The RMS value of this ripple is: Iin RMS + I OUT @ D @ (1 * D) (eq. 14) D is the duty cycle, IinRMS is the input RMS current, and IOUT is the load current. The equation reaches its maximum value with D = 0.5. Loss in the input capacitors can be calculated with the following equation: P CIN + ESR CIN @ IIN RMS 2 (eq. 15) PCIN is the power loss in the input capacitors and ESRCIN is the effective series resistance of the input capacitance. Due to large dI/dt through the input capacitors, electrolytic or ceramics should be used. If a tantalum must be used, it must by surge protected. Otherwise, capacitor failure could occur. Input Start-up Current This equation implies that larger inductor values limit the regulator's ability to slew current through the output inductor in response to output load transients. Consequently, output capacitors must supply the load current until the inductor current reaches the output load current level. This results in larger values of output capacitance to maintain tight output voltage regulation. In contrast, smaller values of inductance increase the regulator's maximum achievable slew rate and decrease the necessary capacitance, at the To calculate the input startup current, the following equation can be used. I INRUSH + C OUT @ V OUT t SS (eq. 16) Iinrush is the input current during startup, COUT is the total output capacitance, VOUT is the desired output voltage, and http://onsemi.com 17 NCP3020A, NCP3020B tSS is the soft start interval. If the inrush current is higher than the steady state input current during max load, then the input fuse should be rated accordingly, if one is used. Output Capacitor Selection I TRAN 2 DV OUT-DISCHG + @ L OUT (eq. 22) C OUT @ V IN * V OUT The important factors to consider when selecting an output capacitor is dc voltage rating, ripple current rating, output ripple voltage requirements, and transient response requirements. The output capacitor must be rated to handle the ripple current at full load with proper derating. The RMS ratings given in datasheets are generally for lower switching frequency than used in switch mode power supplies but a multiplier is usually given for higher frequency operation. The RMS current for the output capacitor can be calculated below: Co RMS + I O @ ra 12 (eq. 17) In a typical converter design, the ESR of the output capacitor bank dominates the transient response. It should be noted that DVOUT-DISCHARGE and DVOUT-ESR are out of phase with each other, and the larger of these two voltages will determine the maximum deviation of the output voltage (neglecting the effect of the ESL). Conversely during a load release, the output voltage can increase as the energy stored in the inductor dumps into the output capacitor. The ESR contribution from Equation 18 still applies in addition to the output capacitor charge which is approximated by the following equation: DV OUT-CHG + Power MOSFET Selection I TRAN 2 @ L OUT (eq. 23) C OUT @ V OUT The maximum allowable output voltage ripple is a combination of the ripple current selected, the output capacitance selected, the equivalent series inductance (ESL) and ESR. The main component of the ripple voltage is usually due to the ESR of the output capacitor and the capacitance selected. V ESR_C + I O @ ra @ ESR Co ) 1 8 @ F SW @ Co (eq. 18) The ESL of capacitors depends on the technology chosen but tends to range from 1 nH to 20 nH where ceramic capacitors have the lowest inductance and electrolytic capacitors then to have the highest. The calculated contributing voltage ripple from ESL is shown for the switch on and switch off below: V ESLON + ESL @ I PP @ F SW D ESL @ I PP @ F SW (1 * D ) (eq. 19) Power dissipation, package size, and the thermal environment drive MOSFET selection. To adequately select the correct MOSFETs, the design must first predict its power dissipation. Once the dissipation is known, the thermal impedance can be calculated to prevent the specified maximum junction temperatures from being exceeded at the highest ambient temperature. Power dissipation has two primary contributors: conduction losses and switching losses. The control or high-side MOSFET will display both switching and conduction losses. The synchronous or low-side MOSFET will exhibit only conduction losses because it switches into nearly zero voltage. However, the body diode in the synchronous MOSFET will suffer diode losses during the non-overlap time of the gate drivers. Starting with the high-side or control MOSFET, the power dissipation can be approximated from: P D_CONTROL + P COND ) P SW_TOT (eq. 24) V ESLOFF + (eq. 20) The output capacitor is a basic component for the fast response of the power supply. In fact, during load transient, for the first few microseconds it supplies the current to the load. The controller immediately recognizes the load transient and sets the duty cycle to maximum, but the current slope is limited by the inductor value. During a load step transient the output voltage initially drops due to the current variation inside the capacitor and the ESR (neglecting the effect of the effective series inductance (ESL)). DV OUT-ESR + DI TRAN @ ESR Co (eq. 21) The first term is the conduction loss of the high-side MOSFET while it is on. P COND + I RMS_CONTROL 2 @ R DS(on)_CONTROL (eq. 25) Using the ra term from Equation 6, IRMS becomes: I RMS_CONTROL + I OUT @ D@ 1 ) ra 2 12 (eq. 26) The second term from Equation 24 is the total switching loss and can be approximated from the following equations. P SW_TOT + P SW ) P DS ) P RR (eq. 27) A minimum capacitor value is required to sustain the current during the load transient without discharging it. The voltage drop due to output capacitor discharge is approximated by the following equation: The first term for total switching losses from Equation 27 includes the losses associated with turning the control MOSFET on and off and the corresponding overlap in drain voltage and current. http://onsemi.com 18 NCP3020A, NCP3020B P SW + P TON ) P TOFF + 1 @ I OUT @ V IN @ f SW @ t ON ) t OFF 2 (eq. 28) where: t ON + Q GD I G1 + Q GD V BST * V TH R HSPU ) R G Q GD V BST * V TH R HSPU ) R G (eq. 29) and: t OFF + Q GD I G2 + (eq. 30) Next, the MOSFET output capacitance losses are caused by both the control and synchronous MOSFET but are dissipated only in the control MOSFET. P DS + 1 @ Q OSS @ V IN @ f SW 2 (eq. 31) Finally the loss due to the reverse recovery time of the body diode in the synchronous MOSFET is shown as follows: P DS + Q RR @ V IN @ f SW (eq. 32) The low-side or synchronous MOSFET turns on into zero volts so switching losses are negligible. Its power dissipation only consists of conduction loss due to RDS(on) and body diode loss during the non-overlap periods. P D_SYNC + P COND ) P BODY (eq. 33) IG1: output current from the high-side gate drive (HSDR) IG2: output current from the low-side gate drive (LSDR) SW: switching frequency of the converter. NCP3020A is 300 kHz and NCP3020B is 600 kHz VBST: gate drive voltage for the high-side drive, typically 7.5 V. QGD: gate charge plateau region, commonly specified in the MOSFET datasheet VTH: gate-to-source voltage at the gate charge plateau region QOSS: MOSFET output gate charge specified in the data sheet QRR: reverse recovery charge of the low-side or synchronous MOSFET, specified in the datasheet RDS(on)_CONTROL: on resistance of the high-side, or control, MOSFET RDS(on)_SYNC: on resistance of the low-side, or synchronous, MOSFET NOLLH: dead time between the LSDR turning off and the HSDR turning on, typically 90 ns NOLHL: dead time between the HSDR turning off and the LSDR turning on, typically 80 ns Once the MOSFET power dissipations are determined, the designer can calculate the required thermal impedance for each device to maintain a specified junction temperature at the worst case ambient temperature. The formula for calculating the junction temperature with the package in free air is: T J + T A ) P D @ R qJA Conduction loss in the low-side or synchronous MOSFET is described as follows: P COND + I RMS_SYNC 2 @ R DS(on)_SYNC (eq. 34) where: I RMS_CONTROL + I OUT @ 2 (1 * D) @ 1 ) ra 12 (eq. 35) TJ: Junction Temperature TA: Ambient Temperature PD: Power Dissipation of the MOSFET under analysis RqJA: Thermal Resistance Junction-to-Ambient of the MOSFET's package As with any power design, proper laboratory testing should be performed to insure the design will dissipate the required power under worst case operating conditions. Variables considered during testing should include maximum ambient temperature, minimum airflow, maximum input voltage, maximum loading, and component variations (i.e. worst case MOSFET RDS(on)). The body diode losses can be approximated as: P BODY + V FD @ I OUT @ f SW @ NOL LH ) NOL HL (eq. 36) Vth Figure 33. MOSFET Switching Characteristics http://onsemi.com 19 NCP3020A, NCP3020B NOLHL NOLLH High-Side Logic Signal Low-Side Logic Signal td(on) RDSmax High-Side MOSFET RDS(on)min tr td(off) tr RDSmax Low-Side MOSFET RDS(on)min td(on) td(off) tf tf Figure 34. MOSFETs Timing Diagram Another consideration during MOSFET selection is their delay times. Turn-on and turn-off times must be short enough to prevent cross conduction. If not, there will be conduction from the input through both MOSFETs to ground. Therefore, the following conditions must be met. t d(ON)_CONTROL ) NOL LH u t d(OFF)_SYNC ) t f_SYNC and (eq. 37) response. The goal of the compensation circuit is to provide a loop gain function with the highest crossing frequency and adequate phase margin (minimally 45). The transfer function of the power stage (the output LC filter) is a double pole system. The resonance frequency of this filter is expressed as follows: f P0 + 1 2 @ p @ L @ C OUT (eq. 38) t (ON)_SYNC ) NOL HL u t d(OFF)_CONTROL ) t f _CONTROL The MOSFET parameters, td(ON), tr, td(OFF) and tf are can be found in their appropriate datasheets for specific conditions. NOLLH and NOLHL are the dead times which were described earlier and are 90 ns and 80 ns, respectively. Feedback and Compensation Parasitic Equivalent Series Resistance (ESR) of the output filter capacitor introduces a high frequency zero to the filter network. Its value can be calculated by using the following equation: f Z0 + 1 2 @ p @ C OUT @ ESR (eq. 39) The NCP3020 is a voltage mode buck convertor with a transconductance error amplifier compensated by an external compensation network. Compensation is needed to achieve accurate output voltage regulation and fast transient Table 2. COMPENSATION TYPES Zero Crossover Frequency Condition fP0 < fZ0 < f0 < fS/2 fP0 < f0 < fZ0 < fS/2 fP0 < f0 < fS/2 < fZ0 The main loop zero crossover frequency f0 can be chosen to be 1/10 - 1/5 of the switching frequency. Table 2 shows the three methods of compensation. Compensation Type Type II (PI) Type III (PID) Method I Type III (PID) Method II Typical Output Capacitor Type Electrolytic, Tantalum Tantalum, Ceramic Ceramic http://onsemi.com 20 NCP3020A, NCP3020B Compensation Type II (PI) This compensation is suitable for electrolytic capacitors. Components of the PI compensation (Figure 35) network can be specified by the following equations: f Z1 + 0.75 @ f P0 f Z2 + f P0 f P2 + f Z0 f P3 + fS 2 (eq. 44) (eq. 45) (eq. 46) (eq. 47) Method II is better suited for ceramic capacitors that typically have the lowest ESR available: f Z2 + f 0 @ f P2 + f 0 @ 1 * sinq max 1 ) sin q max 1 ) sin q max 1 * sin q max (eq. 48) (eq. 49) (eq. 50) (eq. 51) f Z1 + 0.5 @ f Z2 Figure 35. PI Compensation (II Type) R C1 + C C1 + C C2 + R1 + 2 @ p @ f 0 @ L @ V RAMP @ V OUT ESR @ V IN @ V ref @ gm 1 0.75 @ 2 @ p @ f P0 @ R C1 1 p @ R C1 @ f S V ref @ R2 (eq. 40) f P3 + 0.5 @ f S 2 gm The remaining calculations are the same for both methods. R C1 u u (eq. 52) (eq. 53) (eq. 41) C C1 + (eq. 42) 1 2 @ p @ f Z1 @ R C1 1 2 @ p @ f P3 @ R C1 V IN @ R C1 C C2 + (eq. 43) (eq. 54) V OUT * V ref VRAMP is the peak-to-peak voltage of the oscillator ramp and gm is the transconductance error amplifier gain. Capacitor CC2 is optional. Compensation Type III (PID) C FB1 + R FB1 + R1 + 2 @ p @ f 0 @ L @ V RAMP @ C OUT 1 2p @ C FB1 @ f P2 (eq. 55) (eq. 56) Tantalum and ceramics capacitors have lower ESR than electrolytic, so the zero of the output LC filter goes to a higher frequency above the zero crossover frequency. This requires a PID compensation network as shown in Figure 36. There are two methods to select the zeros and poles of this compensation network. Method I is ideal for tantalum output capacitors, which have a higher ESR than ceramic: 1 2 @ p @ C FB1 @ f Z2 V ref (eq. 57) R2 + V OUT * V ref @ R1 (eq. 58) If the equation in Equation 59 is not true, then a higher value of RC1 must be selected. R1 @ R2 @ R FB1 R1 @ R FB1 ) R2 @ R FB1 @ R1 @ R2 u 1 (eq. 59) gm Figure 36. PID Compensation (III Type) http://onsemi.com 21 NCP3020A, NCP3020B TYPICAL APPLICATION CIRCUIT 9- V 18 C IN-1/2 CIN-3/4 CIN-5 C BST VCC BST D1 RG RGS LO 3.3 V Q1 NCP3020A HSDR COMP VSW RFB1 R FB3 C FB C OUT -1 C OUT -2/3 RC C c2 C c1 FB LSDR GND R ISET Q2 R FB2 Figure 37. Typical Application, VIN = 9 - 18 V, VOUT = 3.3 V, IOUT = 10 A Reference Designator CIN-1 CIN-2 CIN-3 CIN-4 CIN-5 CC1 CC2 CFB COUT1 COUT2 COUT3 CBST RC RG RGS RISET RFB1 RFB2 RFB3 Q1 Q2 D1 470 mF 470 mF 22 mF 22 mF 1 mF 82 nF 1.2 nF 6.8 nF 470 mF 22 mF 22 mF 0.1 mF 750 W 8.06 W 10 kW 22.1 kW 4.53 kW 1.0 kW 1.0 kW NTMFS4841N NTMFS4935 BAT54 Value http://onsemi.com 22 NCP3020A, NCP3020B PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AJ -X- A 8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 B 1 S 4 0.25 (0.010) M Y M -Y- G K C -Z- H D 0.25 (0.010) M SEATING PLANE N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 23 NCP3020/D |
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